module Cil2cfg:Build a CFG of a function keeping some information of the initial structure.sig
..end
Not_found
if stmt_opt v
= Nonetype
node_type =
| |
Vstart of |
| |
Vexit of |
| |
VfctIn of |
| |
VfctOut of |
| |
VblkIn of |
| |
VblkOut of |
| |
Vstmt of |
| |
Vtest of |
| |
Vloop of |
val node_type_id : node_type -> int
module VL:sig
..end
type
edge_type =
| |
Enone |
| |
Ethen |
| |
Eelse |
| |
Eback |
| |
EbackThen |
| |
EbackElse |
module EL:sig
..end
module CFG:Graph.Imperative.Digraph.ConcreteLabeled
(
VL
)
(
EL
)
val pretty_edge : Format.formatter -> CFG.E.t -> unit
val set_back_edge : CFG.E.t -> unit
val is_back_edge : CFG.E.t -> bool
val get_test_edges : CFG.t -> CFG.vertex -> CFG.edge * CFG.edge
similar to CFG.succ_e g v
but tests the branch to return (then-edge, else-edge)
Raises Invalid_argument
if the node is not a test.
type
t = {
|
kernel_function : |
|
graph : |
|
stmt_node : |
|
start_id : |
abstract type of a cfg
val new_cfg_env : Db_types.kernel_function -> t
val cfg_kf : t -> Db_types.kernel_function
val cfg_graph : t -> CFG.t
val cfg_start_id : t -> int
val cfg_fct_in_id : t -> int
val cfg_fct_out_id : t -> int
val cfg_exit_id : t -> int
val cfg_start : t -> CFG.V.t
val cfg_fct_in : t -> CFG.V.t
val cfg_fct_out : t -> CFG.V.t
val cfg_exit : t -> CFG.V.t
val cfg_blk_in : t -> Cil_types.stmt -> CFG.V.t
val cfg_blk_out : t -> Cil_types.stmt -> CFG.V.t
val add_node : t -> node_type -> CFG.V.t
val add_edge : t ->
CFG.E.vertex -> edge_type -> CFG.E.vertex -> unit
val init_cfg : Db_types.kernel_function -> t * CFG.V.t * CFG.V.t
module type HEsig =sig
..end
module HE:
module Hpred:HE
(
sig
typet =
Cil_types.predicate Cil_types.named list
end
)
module Hfol:HE
(
sig
typet =
Fol.predicate
end
)
val get_node : t -> node_type -> CFG.V.t
val get_stmt_node : t -> Cil_types.stmt -> CFG.V.t
val cfg_block : t ->
CFG.E.vertex ->
edge_type -> Cil_types.block -> CFG.V.t -> unit
val cfg_stmt : t -> Cil_types.stmt -> CFG.V.t -> unit
Below, we use an algorithm from the paper :
"A New Algorithm for Identifying Loops in Decompilation"
of Tao Wei, Jian Mao, Wei Zou, and Yu Chen,
to gather information about the loops in the builted CFG.
module type WeiMaoZouChenInput =sig
..end
module WeiMaoZouChen:
module LoopInfo:sig
..end
module Mloop:WeiMaoZouChen
(
LoopInfo
)
val mark_loops : LoopInfo.graph -> unit
val loop_stmts : CFG.t -> CFG.vertex -> Cil_types.stmt list
Invalid_argument
if vloop
is not a loop node.Extlib.NotYetImplemented
for non natural loops.val create : Kernel_function.t -> t
Kernel_function.No_Definition
when kf
is a declaration.Extlib.NotYetImplemented
for 'switch' and 'exception'module Printer:
val display : file:string -> ?edge_txt:(CFG.E.t -> string) -> t -> unit
file
with optional text on the edges.